The technology described in this disclosure relates generally to semiconductor devices and more particularly to fabrication of semiconductor devices.
Traditional planar devices often have limitations in terms of miniaturization and choices of suitable materials. As feature sizes of semiconductor devices continue to shrink (e.g., into a sub 50 nm regime), various problems, such as short-channel effects and poor sub-threshold characteristics, often become severe in traditional planar devices. Novel device geometries with enhanced performance, such as three-dimensional device structures (e.g., FinFETs) and hetero-integration of different high-mobility channels for N-MOS and P-MOS devices, have been explored to push toward higher packing densities in devices and circuits.